We describe a two-step-size tapered structure with one defect pair that can markedly enhance the coupling efficiency at the entrance and exit terminals of a planar photonic crystal (PPC) waveguide. PPC waveguides are composed of circular dielectric rods set in two-dimensional square lattices. On the basis of our simulations, we found that the optimized scheme maximizes the power transmission above 90% at a wavelength of 1.55 microm. Besides, one can control the central frequency for optical communications by determining this defect configuration in an optimization procedure. Moreover, by properly adjusting the defect radii in PPC tapers, one can use the PPC circuit as a good reflector.

This study proposes a two-photomask process for fabricating amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) that exhibit a self-aligned structure. The fabricated TFTs, which lack etching-stop (ES) layers, have undamaged a-IGZO active layers that facilitate superior performance. In addition, we demonstrate a bilayer passivation method that uses a polytetrafluoroethylene (Teflon) and SiO2 combination layer for improving the electrical reliability of the fabricated TFTs. Teflon was deposited as a buffer layer through thermal evaporation. The Teflon layer exhibited favorable compatibility with the underlying IGZO channel layer and effectively protected the a-IGZO TFTs from plasma damage during SiO2 deposition, resulting in a negligible initial performance drop in the a-IGZO TFTs. Compared with passivation-free a-IGZO TFTs, passivated TFTs exhibited superior stability even after 168 h of aging under ambient air at 95% relative humidity.

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm 2 /V· s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased. OPEN ACCESSMaterials 2014, 7 5762

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