Traffic Sign Recognition(TSR) is an important element in an Advanced Driver Assistance System(ADAS).However, many studies related to TSR approaches only in normal daytime environment because a sign's unique color doesn't appear in poor environment such as night time, snow, rain or fog. In this paper, we propose a new TSR algorithm based on machine learning for daytime as well as poor environment. In poor environment, traditional methods which use RGB color region doesn't show good performance. So we extracted sign characteristics using HoG extraction, and detected signs using a Support VectorMachine(SVM). The detected sign is recognized by a decision tree based on 25 reference points in a Normalized RGB system. The detection rate of the proposed system is 96.4% and the recognition rate is 94% when applied in poor environment. The testing was performed on an Intel i5 processor at 3.4 GHz using Full HD resolution images. As a result, the proposed algorithm shows that machine learning based detection and recognition methods can efficiently be used for TSR algorithm even in poor driving environment.

SVM, a machine learning method, is widely used in image processing for it's excellent generalization performance. However, to add other data to the pre-trained data of the system, we need to train the entire system again. This procedure takes a lot of time, especially in embedded environment, and results in low performance of SVM. In this paper, we implemented an SVM trainer and classifier in an FPGA to solve this problem. We parlallelized the repeated operations inside SVM and modified the exponential operations of the kernel function to perform fixed point modelling. We implemented the proposed hardware on Xilinx ZC 706 evaluation board and used TSR algorithm to verify the FPGA result. It takes about 5 seconds for the proposed hardware to train 2,000 data samples and 16.54ms for classification for 1360 X 800 resolution in 100MHz frequency, respectively.

SVM is a machine learning method used for image processing. It is well known for its high classification performance. We have to perform multiple MAC operations in order to use SVM for image classification. However, if the resolution of the target image or the number of classification cases increases, the execution time of SVM also increases, which makes it difficult to be performed in real-time applications. In this paper, we propose an hardware architecture which enables real-time applications using SVM classification. We used parallel architecture to simultaneously calculate MAC operations, and also designed the system for several feature extractors for compatibility. RBF kernel was used for hardware implemenation, and the exponent calculation formular included in the kernel was modified to enable fixed point modelling. Experimental results for the system, when implemented in Xilinx ZC-706 evaluation board, show that it can process 60.46 fps for 1360x800 resolution at 100MHz clock frequency.