Limiting the location where electron injection occurs at the cathode interface to a narrower region is the key factor for achieving a highly improved RS performance, which can be achieved by including Ru Nanodots. The development of a memory cell structure truly at the nanoscale with such a limiting factor for the electric-field distribution can solve the non-uniformity issue of future ReRAM.
The characteristics of the atomic
layer deposition (ALD) of SrTiO3 (STO) films were examined
for metal–insulator–metal
capacitors, with Cp-based precursors Sr(iPr3Cp)2 and Cp*Ti(OMe)3 [Cp* = C5(CH3)5] employed as the Sr and Ti precursors, respectively. While
the Sr precursor has a higher reactivity toward oxygen on the Ru substrate
compared with another Ti precursor, with a 2,2,6,6-tetramethyl-3,5-heptanedionato
ligand, which results in the highly Sr excessive STO film, the enhanced
reactivity of the present Ti precursor suppressed the unwanted excessive
incorporation of Sr into the film. A possible mechanism for the Sr
overgrowth and retardation is suggested in detail. By controlling
the subcycle ratio of SrO and TiO2 layers, stoichiometric
STO could be obtained, even without employing a deleterious reaction
barrier layer. This improved the attainable minimum equivalent oxide
thickness of the Pt/STO/RuO2 capacitor to 0.43 nm, with
acceptable leakage current density (∼8 × 10–8 A/cm2). This indicates an improvement of ∼25%
in the capacitance density compared with previous work.
Various array types of 1-diode and 1-resistor stacked crossbar array (1D1R CA) devices composed of a Schottky diode (SD) (Pt/TiO 2 /Ti/Pt) and a resistive switching (RS) memory cell (Pt/TiO 2 /Pt) are fabricated and their performances are investigated. The unit cell of the 1D1R CA device shows high RS resistance ratio ( ≈ 10 3 at 1.5 V) between low and high resistance state (LRS and HRS), and high rectifi cation ratio ( ≈ 10 5 ) between LRS and reverse-state SD. It also shows a short RS time of < 50 ns for SET (resistance transition from HRS to LRS), and ≈ 600 ns for RESET (resistance transition from LRS to HRS), as well as stable RS endurance and data retention characteristics. It is experimentally confi rmed that the selected unit cell in HRS (logically the "off " state) is stably readable when it is surrounded by unselected LRS (logically the "on" state) cells, in an array of up to 32 × 32 cells. The SD, as a highly non-linear resistor, appropriately controls the conducting path formation during the switching and protects the memory element from the noise during retention.
The degradation of ferroelectric (FE) properties of atomic layer deposited Hf0.5Zr0.5O2 films with increasing thickness was mitigated by inserting 1 nm-thick Al2O3 interlayer at middle position of the thickness of the FE film. The large Pr of 10 μC/cm2, which is 11 times larger than that of single layer Hf0.5Zr0.5O2 film with equivalent thickness, was achieved from the films as thick as 40 nm. The Al2O3 interlayer could interrupt the continual growth of Hf0.5Zr0.5O2 films, and the resulting decrease of grain size prevented the formation of non-ferroelectric monoclinic phase. The Al2O3 interlayer also largely decreased the leakage current of the Hf0.5Zr0.5O2 films.
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