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This study proposes a three-level saddle space vector pulse width modulation (SVPWM) strategy based on twolevel SVPWM (TBT_SAPWM) for neutral-point-clamped (NPC) three-level inverters. According to the analysis of the conventional three-level SVPWM strategy based on two-level SVPWM (CTBT_SVPWM) and the proposed TBT_SAPWM strategy, the modulation wave expressions of the two strategies are derived. Compared to the CTBT_SVPWM strategy, each main sector has its own independent area, and determining the main sectors or regions becomes easier with the proposed TBT_SAPWM strategy. Moreover, by optimising the switching states, the proposed TBT_SAPWM strategy makes on-state duration of one selected phase equal to that of the other selected phases in a switching cycle. Therefore, the three-phase modulation waves are saddle waves at the full range of fundamental wave modulation ratios. According to the experimental results in this study, the proposed TBT_SAPWM strategy has better performances in terms of the output harmonics and the neutral-point voltage ripple, compared to the CTBT_SVPWM strategy. The feasibility and effectiveness of the proposed strategy are verified by the experimental platform of an NPC three-level inverter based on the digital signal processor and complex programmable logic device.

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In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.