This work proposes dedicated hardware to real-time cancer detection using Field-Programmable Gate Arrays (FPGA). The presented hardware combines a Multilayer Perceptron (MLP) Artificial Neural Networks (ANN) with Digital Image Processing (DIP) techniques. The DIP techniques are used to extract the features from the analyzed skin, and the MLP classifies the lesion into melanoma or non-melanoma. The classification results are validated with an open-access database. Finally, analysis regarding execution time, hardware resources usage, and power consumption are performed. The results obtained through this analysis are then compared to an equivalent software implementation embedded in an ARM A9 microprocessor.

This work proposes a high-throughput implementation of the Otsu automatic image thresholding algorithm on Field Programmable Gate Array (FPGA), aiming to process high-resolution images in real-time. The Otsu method is a widely used global thresholding algorithm to define an optimal threshold between two classes. However, this technique has a high computational cost, making it difficult to use in real-time applications. Thus, this paper proposes a hardware design exploiting parallelization to optimize the system’s processing time. The implementation details and an analysis of the synthesis results concerning the hardware area occupation, throughput, and dynamic power consumption, are presented. Results have shown that the proposed hardware achieved a high speedup compared to similar works in the literature.

This work proposes a fully parallel hardware architecture of the Naive Bayes classifier to obtain high-speed processing and low energy consumption. The details of the proposed architecture are described throughout this work. Besides, a fixed-point implementation on a Stratix V Field Programmable Gate Array (FPGA) is presented and evaluated regarding the hardware area occupation, processing time (throughput), and dynamic power consumption. In addition, a comparative design analysis was carried out with state-of-the-art works, showing that the proposed implementation achieved a speedup of up to 104× and power savings of up to 107×-times while also reducing the hardware occupancy by up to 102×-times fewer logic cells.

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Experimental tools are a key factor in both academic and industrial research communities to create design evaluations of new networking technologies that involve troubleshooting or changing the planning of deployed networks. Physical Software-Defined Radio (SDR) experimental platforms enable a design solution for the quick prototyping of wireless communication systems. However, SDR-based experimental platforms incur high costs, which leads to scalability limitations in the experimental settings. Having said this, network simulators, emulators, and new testbeds have attracted increasing attention. Emulation-based research prototyping can be distinguished from real communication networks and SDR-based platforms by allowing a tradeoff between cost and flexibility. This paper examines the Mininet-RAN emulation tool, which, as well as Radio Access Network (RAN) modeling, provides a way to test Open RAN Intelligent Controller (RIC) services without the need to deploy an entire RAN infrastructure. The Mininet-RAN creates virtual network elements, such as hosts, L2/L3 devices, controllers, and links, by combining some of the best emulator features, hardware testbeds, and simulators. By running the current code of standard practice Unix/Linux network applications and network stack, the Mininet-RAN enables real-world network data traffic patterns to be delivered to the RIC, regarding the most significant aspect of the dynamic generation of wireless system's KPIs. We provide the basic code of Mininet-RAN for the first two O-RAN Alliance-defined use cases involving V2X and UAV. The xApps are being implemented in O-RAN SC near-RT RIC, with Mininet-RAN which provides a closed-loop validation environment.