This paper describes the design of an implantable system for velocity-selective electroneurogram (ENG) recording. The system, which relies on the availability of multielectrode nerve cuffs (MECs) consists of two CMOS ASICs. One ASIC called the electrode unit (EU) is a mixed analogue/digital signal acquisition system which is mounted directly on an MEC in order to optimize the interface between the two. It is linked to the other ASIC by means of a 5-core cable through which it receives power and commands in addition to transmitting data. The second ASIC, called the monitoring unit (MU) manages the interface between the EUs (each MU can control up to three EUs) and an RF transcutaneous link to the external signal processor. The ASICs are fabricated in 0.8 lm CMOS technology. The EUs measure 3 mm 9 4 mm each and consume 105 mW (35 mW each), while the MU measures 1.5 mm 9 2 mm and consumes 4 mW. The power consumption on the communication channels (including cable losses) between the MU and EUs is 129 mW. A digital communication strategy between the two parts of the implanted system and the external controller is described.

The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. Our proposed memory compression architecture has showed a further size reduction of 15% to 20% on the THUMB code. In this paper we propose to use a high-speed data lossless hardware decompressor to improve the timing performance of the architecture. We simulated the architecture on the SimpleScalar platform and show that for some applications, the time overheads are limited within 5% of the original application. Categories and Subject Descriptors[Embedded Processing]: A method to reduce the code memory size for the embedded system in order to reduce the cost of the whole system.

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Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture – Code Compressed THUMB Processor. In our proposal, Level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator.

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