This study investigates the constraint-force driven control problem of virtual coupling. To solve the constraint force, the explicit equation of vehicle motion with equality constraints is established using the Udwadia–Kalaba approach. First of all, this study introduces a brief overview of virtual coupling concepts in the European Railway Traffic Management System and some scenes of virtual coupling. The control method is proposed to enable the mechanical system to follow the designed constraint. Moreover, the dynamic model for virtual coupling problem is established. Second, combined with the dynamic model, the equation constraint is designed to make the rail vehicle movenment reach the control objective. By solving the equation based on the Udwadia–Kalaba approach, the control inputs that can render the vehicle to move along the desired trajectory. Third, numerical simulation results demonstrate the effectiveness of the proposed method in virtual coupling problem.

Purpose The purpose of this paper is to reduce the difficulty of model predictive control (MPC) deployment on FPGA so that researchers can make better use of FPGA technology for academic research. Design/methodology/approach In this paper, the MPC algorithm is written into FPGA by combining hardware with software. Experiments have verified this method. Findings This paper implements a ZYNQ-based design method, which could significantly reduce the difficulty of development. The comparison with the CPU solution results proves that FPGA has a significant acceleration effect on the solution of MPC through the method. Research limitations implications Due to the limitation of practical conditions, this paper cannot carry out a hardware-in-the-loop experiment for the time being, instead of an open-loop experiment. Originality value This paper proposes a new design method to deploy the MPC algorithm to the FPGA, reducing the development difficulty of the algorithm implementation on FPGA. It greatly facilitates researchers in the field of autonomous driving to carry out FPGA algorithm hardware acceleration research.

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