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This paper presents the design and implementation of an extended-counting incremental sigma–delta ADC (IDC) with hardware-reuse technique. The proposed ADC architecture is a cascaded configuration of a second-order IDC and a two-stage cyclic ADC. The operation of the ADC consists of the “coarse phase” and the “fine phase”. In the “coarse phase”, the circuit works as an IDC to achieve the most significant bits (MSBs) and produce the residue voltage. Then in the “fine phase”, it is reused and changed to work as a cyclic ADC to quantize the residue voltage and achieve the least significant bits (LSBs). Eventual digital output is achieved by combining the two parts together. The utilization of extended-counting technique significantly reduces the conversion time and increases the conversion rate, and the hardware-reuse technique removes the demand for additional circuit area. The ADC is designed in 0.5[Formula: see text][Formula: see text]m CMOS process, which has a conversion rate of 43.48[Formula: see text]kS/s with oversampling ratio (OSR) of 23 and achieves 84.83[Formula: see text]dB SNDR and 13.799-bit ENOB. It consumes 2.4[Formula: see text]mW with a 5[Formula: see text]V voltage supply, and the FOM is 3.87[Formula: see text]pJ/step.

In this study, an event-driven detection method based on pseudo-differential self-timed inverter-based incremental sigma-delta analogue-to-digital converter (IDC) is proposed and analysed, which is adapted for sparse signal measurement. A judgment module is implemented to detect whether the input signal of the measurement system is beyond a threshold or not. The input signal will be converted by the IDC only when it is beyond the threshold. A pseudo-differential self-timed inverterbased IDC is also proposed in the event-driven detection technique. The proposed event-driven detection technique is designed and simulated with 1.5-V supply voltage. The IDC achieves 12.8-bit ENOB at 2-KS/s conversion rate and consumes 45 μW. Its figure-of-merit is 3.1 pJ/step and input range is 0-2.4 V. The sparse signal measurement system with the proposed event-driven detection method based on self-timed IDC is implemented. The average power consumption of the system is related to the event ratio. With the event ratios of 10, 20 and 30%, its power consumption will be 30, 34 and 37 μW, respectively. The eventdriven detection method improves the power efficiency of the sparse signal measurement system.