Although it is well-known that the size can influence the surface plasmon resonance property of coinage metals and the electronic state of the Mott–Schottky junction formed at the metal/semiconductor interface, insights into how the size can be exploited to optimize the photocatalytic activity and selectivity of metal/semiconductor composites are lacking. Here we utilize operando SERS spectroscopy to identify the size effect on the electron-transfer dynamics and the direction at the Au/TiO2 interface. This effect was characterized by the photocatalytic reduction sites of p-nitrothiophenol, which were self-tracked with the SERS spectra from Au nanoparticle and inverse-opal structured TiO2, respectively. The size-dependent unidirectional/bidirectional transfer of photoinduced electrons at the Au/TiO2 interface was revealed by operando SERS spectroscopy, which enables the rational tuning of the reduction selectivity.

Amorphous MoO3−x nanosheets were fabricated by the room‐temperature oxidation of molybdenum powder with H2O2, followed by light‐irradiation reduction in methanol. When applied as a substrate for surface‐enhanced Raman spectroscopy (SERS), these nanosheets exhibit higher sensitivity than the crystalline counterpart for a wide range of analytes. Moreover, the SERS activity remains stable on repeated oxygen insertion/extraction. In contrast, the performance of crystalline MoO3−x continuously deteriorates on successive redox treatments. This unique SERS activity allows the recycling of the substrate through an H2O2‐based Fenton‐like reaction. More importantly, the non‐invasive SERS was unprecedentedly used for the self‐diagnosis of amorphous MoO3−x as a more selective photocatalyst than its crystalline counterpart.

In this paper, a design and optimization of a 4-bit absolute value detector is realized by using the CMOS technique, transmission gates, and the traditional comparator, which can compare the two positive input values all expressed in binary form. To optimize the overall performance of the absolute value detector, this paper chooses to minimize the number of transistors and simplifies the circuit through logical analysis. As for calculating the overall delay and energy consumption, critical path identification is also studied and analyzed in this paper. Based on the theory of path effort and path parasitic delay, the grid capacitance and resistance are introduced into the calculation of inverter ratios. To achieve various optimization objectives, this study also combines the grid size and power supply voltage scaling techniques to reduce the delay and energy of the circuit, and finally finds the minimum energy loss at a 1.5x delay. The overall delay and energy can be expressed by the multiple of the unit size inverter of that. As a compromise, a minimum delay of 1.5 times is selected to reduce energy consumption by 39.16 %.

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