No abstract

The aim of this study was to develop a flexible package technology using laser-assisted bonding (LAB) technology and an anisotropic solder paste (ASP) material ultimately to reduce the bonding temperature and enhance the flexibility and reliability of flexible devices. The heat transfer phenomena during the LAB process, mechanical deformation, and the flexibility of a flexible package were analyzed by experimental and numerical simulation methods. The flexible package was fabricated with a silicon chip and a polyimide (PI) substrate. When the laser beam was irradiated onto the flexible package, the temperatures of the solder increased very rapidly to 220 °C, high enough to melt the ASP solder, within 2.4 s. After the completion of irradiation, the temperature of the flexible package decreased quickly. It was found that the solder powder in ASP was completely melted and formed stable interconnections between the silicon chip and the copper pads, without thermal damage to the PI substrate. After the LAB process, the flexible package showed warpage of 80 μm, which was very small compared to the size of the flexible package. The stress of each component in the flexible package generated during the LAB process was also found to be very low. The flexible device was bent up to 7 mm without failure, and the flexibility can be improved further by reducing the thickness of the silicon chip. The bonding strength and environmental reliability tests also showed the excellent mechanical endurance of the flexible package.

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.