In this paper, we propose a novel normally-off MIS-HEMT structure, mainly using Split-Gate Technology, Piezo Neutralization Technique (PNT), Field Plate Technology. By analyzing the effects of different Al composition in the PNT layer and buffer layer on devices, the Piezo Neutralization Technique is optimized. The current turn-on/off is controlled by changing gate voltage to regulate the horizontal conduction band between the double gates. The effects of gate length and block barrier size between the double gates on device performance are studied. Through two-dimensional device simulation, the operation principle and internal mechanism are analyzed. An improved device with good performance is presented. The threshold voltage Vth is 4.1 V, the peak transconductance is 0.3 S/mm, the maximum drain current is 1.1 A/mm and the breakdown voltage is 1200 V.

The Dual-Direction Silicon Controlled Rectifier (DDSCR) device has dual-direction electrostatic protection function and strong current discharging ability, which is widely used in ESD on-chip protection. In this paper, a high performance symmetric high voltage Dual-Direction Silicon Controlled Rectifier with floating P+ (HVDDSCR_FP+) is designed for CAN bus under 0.18 μm BCD process. In order to predict and verify the ESD performance of the device, TCAD two-dimensional device simulation and Transmission Line Pulse (TLP) test system were used. The experimental results show that the HVDDSCR_FP + structure has not only symmetrical positive and reverse I-V curves, but also the characteristics of high holding voltage and high failure current. Compared with the traditional HVDDSCR, HVDDSCR_FP+, at 25V forward and reverse trigger voltages (Vt), has increased its holding voltage (Vh) from 12V to 20V, failure current (It2) from 5A to 35A. In the actual tape-out process, it is found that the width of the N-well has a great influence on the performance of the device. After analyzing the reason and improving it, the leakage current of the device is reduced from μA level to nA level.

Purpose As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time. Design/methodology/approach Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness. Findings The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+. Originality/value Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.