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The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm x 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm x 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology. INTRODUCTIONTSV-based 3DIC has been not only recognized as one of the key interconnection technologies in 3DIC packages, but also considered as a promising solution to improve packaging density, power consumption, system bandwidth with effective form factor reduction and attractive cost model for the packaging of semiconductor devices [1][2][3][4][5][6]. Besides, such a technology enables the stacking integration of dissimilar functional circuit chips and transforms the stacked chips into a system with multi-functional features.Thermal stress will inevitably be developed in the vicinity of TSV due to the mismatch in thermal expansion coefficient (CTE) between TSV Cu and surrounding Si during the process flow when the system encounters temperature rise and fall, such as the copper annealing process. Such developed stress could have a significant impact on the device performance. Reducing the Cu volume with smaller TSV CD is an effective way to alleviate the impact of such TSV-induced stress. In this work, TSV stress reduction is demonstrated by using high aspect ratio Cu TSV, 2 μm x 30 μm, in 28 nm chips with high yield 3DIC integration and foundry technology.TSV ELECTRICAL CHARACTERISTICS