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16M-superSRAM with 0.98 pm2 is developed by existing 0.15 pm DRAM processes. As a result, the standby current and random access time of fabricated 16M-superSRAM are about 0.2 @/chip and 43 ns at RT. As superSRAM has a cylindrical stacked capacitor at each node, very high tolerance for SER (soft error rate) is expected as compared with conventional 6Tr-SRAMs. By alpha ray irradiated experiments, an SER free feature of superSRAM is confirmed for the first time.

We investigated a bipolar transistor with a buried layer formed by high-energy ion implantation without the epitaxitial silicon layer growth. We focused mainly on the reduction of junction leakage current related to implantation damages, which could be achieved by rapid thermal annealing. Consequently, the maximum current gain of 155 and the cutoff frequency of 17.3 GHz were achieved with B V CE0=5.0 V. Moreover, this fabrication process is applicable to the conventional complementary metal oxide semiconductor (CMOS) process with the retrograde twin wells without additional process steps. Therefore, this technique can be very promising for the fabrication of subhalf-micron BiCMOS LSIs.

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