In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin 9 2 -i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.

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Application examples of charge-domain logic are described. To investigate the characteristics and possibilities of charge-domain logic, prototype implementations are made for full adder and CRC checker designs by standard CMOS, and fabricated by MOSIS 1.5u, double overlapping poly, and double metal technology. Those application designs require less than 8 steps of charge transfer so that no special fabrication process is required. Some of the results from evaluation experiment for both designs are also included.

A multiplication type D/A convertor based on the new principles of charge-domain operations is proposed. The D/A convertor has a linear structure of overlapping gates. The design was fabricated by a standard 1.5um CMOS process. Evaluation results of the two types of D/A conversion experiment are presented. By simple charge accumulation a relatively high, more than 11-bit, resolution is observed. For a successive charge splitting type D/A conversion, although our current evaluation results only show 5-bit resolution, we found possible clues for future improvements.

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