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Abstract-We report power-aware 65-nm node CMOS device technology suitable for body biasing scheme. For highperformance CMOS, both channel and halo profiles have been optimized to enhance the body-bias effect of 45-nm gate length devices. Standby leakage reduction without device reliability compromise has been demonstrated with simultaneous voltage control of body bias and power supply. Moreover, high-k gate dielectric "HfSiON" has been adopted to reduce both gate leakage and GIDL, which are the dominant standby leakage components of low standby power CMOS.

A face-to-face chip stacking isolator structure, which makes it easy to enhance the insulation voltage, is proposed. Transmitter (Tx) and receiver (Rx) chips, each of which has a coil, are stacked and communicate through a magnetic coupling of the coils. The die attach film sandwiched by the two chips not only bonds the chips but also enhances the insulation voltage by taking advantage of its thickness. With test chips, the breakdown voltage of 7kV RMS is demonstrated and >20-year lifetime with a working voltage of 1.5kV is estimated by extrapolation of time-dependent dielectric breakdown results.I.

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