No abstract

We present a SPAD Verilog-A model accounting for the temporal avalanche buildup and its statistics. This physics-based approach is benched on TCAD mixed-mode analyzing predictions, as well as measurements. The buildup that can be in the order of 50-100ps, affects the pulse width distribution which is experimentally verified. Furthermore, we address in details the voltage swing across the device from the avalanche to its quenching, with a view on power consumption impact. This model can help a chip designer to optimize circuits for quenching the diode.I.