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In this paper, a new area and delay minimization architecture is proposed for rank-1 update matrix–matrix multiplication whose inputs are double precision floating point number. The architecture design is based on pipelined multiplication which handles matrix of arbitrary sizes; the processing data are stored in dedicated on-chip BRAM. This minimization is introduced to designers as a trade-off between bandwidth and local memory. Analysis is presented for the design parameters optimal choice. In addition, Vedic matrix multiplication architecture is given in order to explore the variations in power, delay and memory. The hardware architecture is described in Verilog HDL synthesized for a family virtex-6 and device xc6vlx240t FPGA, which scale more than 40 processing elements. Various parameters like LUTs, Slices, bonded IOBs, frequency, DSP48E1S, delay, Power, CPU Completion time and Memory usage are analysed. Rank 1 update consumes a power of 2.520 watt and has a delay of 5.277 ns respectively. Comparing other rank-1 multiplication methods our proposed algorithms uses 15% less area resources and improves the delay in 12%.

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