In reality, signals exist in analog format. The digital circuits are more convenient than analog circuits with respect to processing speed and efficiency in transmission. Hence there is a great demand for ADC converters. The typical Flash ADC contains resistor ladder circuit, comparator and code converter. The most advantageous parameter of Flash ADC is its speed. Hence it can be used in variety of applications such as micro electronics, wireless sensor networks, transceivers. Flash ADC still suffers from minimum resolution and consumes large amount of power. However these are due to its complexity in terms of chip area requirement in comparison with other ADCs. This new technique of four bit Flash ADC using TIQ comparator is implemented here. Here, a comparison is brought between the input signals with internal built threshold using TIQ comparators. It avoids the too much resistor usage in ladder network. In general, 2N -1 number of TIQ comparators is required to design N-bit flash ADC. TIQ output was encoded into binary by an encoder. A new MUX based encoding technique has been used to enhance the conversion speed for achieving highest sampling rate with low power dissipation. The design is simulated in Mentor Graphics environment using 130nm technology and result shows a deep reduce in the power consumption i.e.0.833µW and conversion speed 15.393ns for 4-bit ADC.

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Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified greywolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

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