The thermal accumulation improvement is based on laser epitaxial growth for monolithic 3D-ICs manufacturing. We propose one structure which has a thermal conduction layer such as Cu in ILD oxide layer. To reduce the Via depth and ILD oxide thickness can improve the re-crystallization quality for upper Si layer. With the conduction Cu layer, the Via depth can reduce to 200 nm, and the maximum temperature of the 1 8t layer poly gate and source/drain maintains as low as .....,320K and .....,350K, respectively, for laser re-crystallization annealing.

The channel strain enhancement by embedded stressor in source/drain (S/D) had been already the mainstream process for state-of-the-art CMOS technology [1] [2]. The embedded stressor usually are SiGe and/or silicon carbon alloy (Si:C) to increase the channel strain and performance with the lattice mismatch [3] [4]. Due to the smaller lattice constant of carbon, 1% carbon added in the Si channel yields the same strain as 10% Ge added into the SiGe layer. In order to benefit electron mobility enhancement of NFET, the smaller lattice of carbon is incorporated in S/D to induce uniaxial tensile strain in the channel. Furthermore, we report the carbon was incorporated with biaxial tensile strained-Si for S/D engineering in this work.The st-Si:C (strained-Si:C) ( Fig. 1) and Si:C NMOSFETs were fabricated in our standard 4" process line. The relaxed Si 0.8 Ge 0.2 layers (1 μm thick) with a uniform Ge content (20%) were grown by UHVCVD on an epitaxial graded Si 1-x Ge x layers (1 μm thick) with the Ge content from 0 to 20% at 600 using Silane (SiH 4 ) and Germane (GeH 4 ) precursors. Then, the ~20 nm st-Si channel with in-situ carbon incorporation is grown on the relaxed Si 0.8 Ge 0.2 virtual substrate [5]. The Methylsilane (CH 3 SiH 3 ) as the carbon precursor makes more substitutional carbon than that of Ethylene (C 2 H 4 ). To reduce the thermal budget, the gate oxide (TEOS, tetraethylorthosilicate) with a thickness of ~30 nm was deposited at 700 o C and the transistors are fabricated. The S/D activation temperature and time are used 800 o C and 15 min, respectively.The transmission electron microscopy (TEM) image of st-Si:C channel device after thermal budget of transistor fabrication process (Fig. 2). The thickness of st-Si:C channel keeping ~20 nm indicates that the Ge outdiffusion is not happened significantly after the device process. The outdiffusion of the arsenic is measured by SIMS from highly doping S/D in vertical direction (Fig. 3), as well as infers similar behavior into channel in lateral direction is also investigated. The vertical diffusion of arsenic in the st-Si:C devices is retarded as compared to the bulk Si devices, while st-Si device has the enhanced diffusion [6][7]. This indicates st-Si NMOSFET has more serious short channel effect than bulk Si and st-Si:C devices. Note that carbon can retard Ge outdiffusion into channel in this implantation condition (Fig.3), to obtain abrupt strainedSi:C/relaxed SiGe buffer heterojunction [8]. The similar sheet resistance (Rs) and contact resistance (Rc) of st-Si:C S/D were obtained with different carbon concentration (Fig. 4). For Si:C/Si which is without the strain by underneath relaxed SiGe buffer, the higher resistance was obtained with carbon increasing (Fig. 4). The st-Si:C and Si:C/Si with C=0.46% have similar resistance (Rc & Rs). This indicates the dopant activation is less in Si:C/Si with carbon increasing but it is improved in st-Si:C by strain from underneath relaxed SiGe. The st-Si:C NMOSFET with carbon ~0.25% has the saturation current enhancemen...

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