In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.

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This work describes a new DRAM cell technology, WIWNxP-gate NMOS memory cell (MC) transistors, which has been integrated into dual-gate CMOS process. Operation speed, data retention time (tREF), and reliability of high speed DRAM are dramatically improved by Pi-gate NMOS cell having low-resistance polymetal word line (WL). Transistor performance in periphery circuit is enhanced by dual-gate CMOSFETs formed with low temperature process. These technologies offer excellent scalability and fully operating DDR-I1 SDRAM test chips have been obtained.

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