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noise analysis, power ground pins assignment and power plan generation. We reason that the power plan is built for normal mode Power noise has become one of the main culprits in failing chips operation and maybe too weak during test mode. Next, a brief in SoC designs. As power consumption during scan test can be overview of existing test power reduction methods is presented. We several times higher than during normal operation, it must be dealt feel that most of the proposed methods are either not practical or lack with properly during implementation and testing stages. In this paper, EDA tool support. We then present our in-house power noise we share some of the test power related experiences we gained analysis tool that can do what-if analysis for test mode power, and through the development of NetComposer platform design. We how we apply good DFT practice on the NetComposer-I platform demonstrate how good power analysis and DFT can help avoid design to solve test mode power noise issue. ATE test results potential power noise issue during test.indirectly prove the usefulness of our proposed methodology.