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A 90 nm generation logic technology with Cu / low-k interconnects is reported. SOnm transistors are employed gate oxide with 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 pA/pm and 360 pA/pm for NMOS and PMOS respectively, while generic transistors have currents of 640 pA/pm and 260 pA/pm respectively. Low power process using high-k gate dielectrics and SO1 process are also provided in this technology. The low-k SiOC material with 2.9 in the.k value is used for 9 layers of dual damascene Cu / low-k interconnects. The effective k (ken) value of interconnect is about 3.6. Fully working 6-T S U M cell with an area of 1.1 pm2 and SNM value of 330mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppmiv.

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The thermal stability of titanium disilicide (TiSi2) film under dielectric capping layers was studied. Dielectric capping layers prevent changes in sheet resistance and the film stress of the TiSi2 film during annealing at 900°C. The enhancement of thermal stability of the TiSi2 film was dependent on the nature of dielectric; thermal stability of the TiSi2 film was enhanced more effectively by the plasma-enhanced silicon nitride (PE-SiN) capping layer rather than the undoped silicate glass (USG; S1O2) capping layer. The dependence of thermal stability of the TiSi2 film with the nature of dielectrics was due to the difference in stress of dielectrics at anneal temperature. At 900°C, stress of the USG film was nearly twice of that of the PE-SiN film. Agglomeration of the TiSi2 film under the dielectric capping layer at high temperature annealing can be explained by a diffusional flow of atoms called Nabarro-Herring Microcreep. As the size of Ti-polycide lines becomes smaller, the nature of the dielectric film on the TiSi2 film will be more important for achieving thermal stability.