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We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4-bit, 1-GS/s prototypes in 0.13-μm and 65-nm CMOS processes, which show a small area (0.015 mm 2 ) and small power consumption (< 2.4 mW).

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This work introduces a 2-D phased array architecture that is suitable for high power radiation at mm-Wave and Terahertz frequencies. We address the challenge of signal generation above the cut-off frequency of transistors by presenting a radiation method based on the collective performance of a large number of synchronized sources. As theory shows, both frequency locking/ tuning and beam steering can be independently achieved by manipulating the local coupling between the nearest neighbors. This control method results in a dynamical network that is insensitive to array dimensions and is scalable to the point that can achieve a level of output power and spectral purity beyond the reach of conventional sources. To demonstrate the concept, we implement a 4 4 version of this phased array at 340 GHz using a 65 nm bulk CMOS process. The paper presents the design and implementation of the oscillators, couplings and the integrated antennas. The measured results at 338 GHz reveal a peak equivalent isotropically radiated power (EIRP) of +17.1 dBm and a phase noise of -93 dBc/Hz at the 1 MHz offset frequency. This chip presents the first fully integrated terahertz phased array on silicon. Furthermore, the output power is higher than any lens-less silicon-based source above 200 GHz and the phase noise is lower than all silicon radiating sources above 100 GHz.