In this paper, we study the single machine vector scheduling problem (SMVS) with general penalties, in which each job is characterized by a d-dimensional vector and can be accepted and processed on the machine or rejected. The objective is to minimize the sum of the maximum load over all dimensions of the total vector of all accepted jobs and the rejection penalty of the rejected jobs, which is determined by a set function. We perform the following work in this paper. First, we prove that the lower bound for SMVS with general penalties is α(n), where α(n) is any positive polynomial function of n. Then, we consider a special case in which both the diminishing-return ratio of the set function and the minimum load over all dimensions of any job are larger than zero, and we design an approximation algorithm based on the projected subgradient method. Second, we consider another special case in which the penalty set function is submodular. We propose a noncombinatorial ee−1-approximation algorithm and a combinatorial min{r,d}-approximation algorithm, where r is the maximum ratio of the maximum load to the minimum load on the d-dimensional vector.

Ultra-high-speed object detection and tracking are crucial in fields such as fault detection and scientific observation. Existing solutions to this task have deficiencies in processing speeds. To deal with this difficulty, we propose a neural-inspired ultra-high-speed moving object filtering, detection, and tracking scheme, as well as a corresponding accelerator based on a high-speed spike camera. We parallelize the filtering module and divide the detection module to accelerate the algorithm and balance latency among modules for the benefit of the task-level pipeline. To be specific, a block-based parallel computation model is proposed to accelerate the filtering module, and the detection module is accelerated by a parallel connected component labeling algorithm modeling spike sparsity and spatial connectivity of moving objects with a searching tree. The hardware optimizations include processing the LIF layer with a group of multiplexers to reduce ADD operations and replacing expensive exponential operations with multiplications of preprocessed fixed-point values to speed up and minimize resource consumption. An accelerator is designed with the above techniques, achieving 19 times acceleration over the serial version after 25-way parallelization. A processing system for the accelerator is implemented on the Xilinx ZCU-102 board to validate its functionality and performance. Our accelerator can process more than 20,000 spike images with 250 × 400 resolution per second with 1.618 W dynamic power consumption.

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