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Several promising implementations of quantum computation rely on a Linear Nearest Neighbor (LNN) architecture, which arranges quantum bits on a line, and allows neighbor interactions only. Therefore, several specific circuits have been designed on an LNN architecture. However, a general and efficient conversion method for an arbitrary circuit has not been established. Therefore, this paper gives an efficient conversion technique to convert quantum circuits to an LNN architecture. When a quantum circuit is converted to an LNN architecture, the objective is to reduce the size of the additional circuit added by the conversion and the time complexity of the conversion. The proposed method requires less additional circuitry and time complexity compared with naive techniques. To develop the method, we introduce two key theorems that may be interesting on their own. In addition, the proposed method also achieves less overhead than some known circuits designed from scratch on an LNN architecture.

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The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an applicationspecific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized 8.5mm × 8.5mm, consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V. With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps.

Abstract. Stability of nanostructures of epoxy/acrylic triblock copolymer blends was studied. PMMA-b-PnBA-b-PMMA triblock copolymers (acrylic BCPs) having several compositions on the ratio of the block chains and the molecular weight were initially prepared and were blended with diglycidyl ether of bisphenol-A epoxy thermosets. The blends were cured using phenol novolac with tri phenyl phosphine (TPP) as the catalyst. Several nanostructures, such as spheres, cylinders, curved lamellae, were observed in the cured blends. The nanostructures were controlled by the molecular weight of the immiscible PnBA-block chain and the ratio of the PnBA in the blends. Moreover, the effect of the gel time to the nanostructures was examined by altering the trace amount of the TPP in the blends. The types of the nanostructures were almost kept irrespective of the gel time of the blends when the composition of the blends was maintained. This suggested the stability of the nanostructures of the epoxy/acrylic BCP blends made via the self-assembly mechanism, therefore a phase diagram of the cured blends was proposed.