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A new in-situ timing-error prediction and prevention technique named HEPP is proposed for mitigating the impact of PVT variations on ultra-low-voltage digital designs. Compared to the prior techniques including Razor and Canary flip-flop, the proposed technique eliminates the hold-time constraint and is able to deal with errors caused by infrequently activated critical paths and fast dynamic variations. It has low overhead and is applicable to general digital designs. The experimental results of applying the proposed HEPP technique to a FFT processor show 122% performance improvement or 88% energy reduction compared to the conventional worst-case design.