Despite significant efforts to improve the treatment of tuberculosis (TB), it remains a prevalent infectious disease worldwide owing to the limitations of current TB therapeutic regimens. Recent work on novel TB treatment strategies has suggested that directly targeting host factors may be beneficial for TB treatment. Such strategies, termed host-directed therapeutics (HDTs), focus on host-pathogen interactions. HDTs may be more effective than the currently approved TB drugs, which are limited by the long durations of treatment needed and the emergence of drug-resistant strains. Targets of HDTs include host factors such as cytokines, immune checkpoints, immune cell functions, and essential enzyme activities. This review article discusses examples of potentially promising HDTs and introduces novel approaches for their development.

DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/ underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.

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In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.