A novel VCO auto frequency calibration(AFC) technique is presented in this paper. It provides ultra-fast and high-precision search for an optimum VCO discrete tuning curve among a group of frequency sub-bands in the PLL frequency synthesizer. The calibration circuit consists of a table of frequency (TOF) and a finite state machine (FSM). Asynchronous work of TOF and FSM makes it possible to realize ultrafast and high-precision calibration simultaneously. TOF affords the high-precision of the calibration and FSM with a high-speed clock offers the ultra-fast search. A 2.8G-3.5GHz Fractional-N PLL incorporating the proposed calibration technique is implemented in 55nm CMOS process. The measured calibration time for a 5-bit capacitor bank is 90ns for a frequency resolution of 203KHz. Such small calibration time significantly reduces the effects of calibration time on the total lock time of the PLL.

A novel high-swing Class-C VCO with an amplitude feedback loop is presented. The amplitude feedback loop is used to ensure the start-up of the VCO which also makes the proposed VCO always have an optimal phase noise against the PVT variations automatically. The proposed circuit is implemented in a 65 nm CMOS process. The VCO has exhibited a measured phase noise of −128.6 dBc/Hz at 1 MHz offset from the 1.52 GHz carrier frequency with a 1.4 mW power consumption. The variation of measured phase noise at 1 MHz offset is less than 2.3% while temperature changes from −40 • C to 100 • C.