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The major drawback of an on-chip network is the strongly decreased timing predictability due to the dynamic routing. While for some special applications, such as distributed shared memory (DSM) and multi-mode cryptosystems, it's not necessary to introduce the dynamic routing mechanism between multiple processing elements (PEs) due to their different communication features. Therefore, we propose a hierarchical topology which is scalable, resource-efficient, latency-predictable, compact and easy to implement due to its simple interconnect. In a hierarchical topology, the router can be designed statically so that the transport latency of packets transmitted via the on-chip network becomes much easier to predict as long as the deadlock and starvation problems have been prevented.In this paper, we analyze the local transport latency and the global transport latency of our application specific NoC design and show that they are predictable and bounded within a boundary derived from the proposed prediction equations.I.

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The proposed system integrates the IEEE 1588 standard with the Pulse Per Second (PPS) mechanism to improve the accuracy of timing synchronization of the multiple nodes. A reference implementation for the virtual orchestra was given and introduced to evaluate the performance. It operates in the form of a character device driver and the application interface (API) was built for a programmer to use this proposed system. The experimental results show that the accuracy achieves the degree of several microseconds and the proposed system is acceptable for the application.