Summary A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias VDD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm2.

A varactorless divide‐by‐4 injection‐locked frequency divider (ILFD) with LC resonator is designed. The ILFD uses the parasitic capacitors and the inductor architecture to construct a dual‐resonance resonator. The ILFD has two locking ranges associated with the dual‐resonance resonator. The locking range of the ÷4 ILFD is wider than conventional single‐band ÷4 LC‐tank ILFD because of overlapped locking ranges. The designed single‐stage ÷4 ILFD was fabricated in the TSMC 0.18 μm 1P6M CMOS process. At the incident power of 0 dBm, the locking range is 6.6 GHz from 7.3 to 13.9 GHz at the power consumption of 5.59 mW.