Network-on-chip (NoC) is an alternative approach to traditional communication methods for system-on-chip architectures. Irregular topologies are preferable for the application specific NoC designs as they offer huge optimisation space in contrast to their regular counterparts. Generating an application-specific topology as part of the synthesis flow of a NoC architecture is a challenging problem as there may be several topology alternatives, each of which may be superior to the others based on the different objective criteria. In this study, the authors tackle at this problem and propose a heuristic and a genetic algorithm-based methods. The heuristic method, called TopGen, is a two-phase application-specific topology generation algorithm aiming to minimise the energy consumption of the system. TopGen first decomposes the given application into clusters based on the communication traffic. It then maps the clusters onto the routers and connects them in such a way that the communication cost of the network is minimised. The second algorithm, called GA-based topology generation algorithm-based topology generation algorithm (GATGA), is based on a genetic algorithm, which initially creates a set of solutions and uses genetic operators to reproduce new topologies from them. The authors compared our algorithms with existing methods through several multimedia benchmarks and custom generated graphs. TopGen and GATGA obtained better results than previous methods with negligible area and link length overheads.

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When designing a Network-on-Chip (NoC) architecture, designers must consider various criteria such as bandwidth, performance, energy consumption, cost, re-usability, and fault tolerance. In most of the design efforts, it is very difficult to meet all these interacting constraints and objectives at the same time. Some of these parameters can be optimised and met easily by regular NoC topologies due to their re-usability and fault-tolerance capabilities. On the other hand, other parameters such as energy consumption, performance, and chip area can be better optimised in irregular NoC topologies. In this work, the authors present a novel two-step method that combines the advantages of regular and irregular NoC topologies. In the first step, the authors' method generates an energy and area optimised irregular topology for the given application by using a genetic algorithm. The generated topology uses the least amount of routers and links to minimise the area and energy; thus, it offers only one routing path between communicating nodes. Therefore, it does not fault tolerant. In the second step, their method maps the generated irregular topology to a reconfigurable mesh topology to make it fault tolerant. The detailed simulation results show the superiority of the proposed method over the existing work on several multimedia benchmarks.

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