Graphene has attracted considerable interest as a potential new electronic material [1][2][3][4][5][6][7][8][9][10][11] . With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics [12][13][14][15][16][17][18] . However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance [19][20][21] . Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co 2 Si-Al 2 O 3 core-shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the selfalignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA mm 21 ) and transconductance (1.27 mS mm 21 ) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of f T 5 100-300 GHz, with the extrinsic f T (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic f T of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths 10 .With the highest carrier mobility, exceeding 200,000 cm 2 V 21 s 21 (ref. 8), and many other desirable properties, including a large critical current density (,2 3 10 8 A cm 22 (ref. 22)) and a high saturation velocity (5.5 3 10 7 cm s 21 (ref. 11)), graphene has significant potential for high-speed electronics to offer excellent radio-frequency characteristics with very high cut-off frequency (f T ). Importantly, recent studies have demonstrated graphene transistors operating in the gigahertz regime [12][13][14][16][17][18] with a record of f T 5 100 GHz (ref. 13). However, the reported radio-frequency performance so far is still far from the potential that the graphene transistors may offer, and is primarily limited by two adverse factors in the device fabrication process.The first limitation is associated with the severe mobility degradation resulting from the graphene-dielectric integration process, which introduces substantial defects into pristine graphene lattices 20,23 . To overcome this, we have recently developed a strategy to integrate high-quality, high-dielectric-constant dielectrics with graphene using a physical assembly approach without in...

Metal oxides are emerging as important materials for their versatile properties such as high-temperature superconductivity, ferroelectricity, ferromagnetism, piezoelectricity and semiconductivity. Metal-oxide films are conventionally grown by physical and chemical vapour deposition. However, the high cost of necessary equipment and restriction of coatings on a relatively small area have limited their potential applications. Chemical-solution depositions such as sol-gel are more cost-effective, but many metal oxides cannot be deposited and the control of stoichiometry is not always possible owing to differences in chemical reactivity among the metals. Here we report a novel process to grow metal-oxide films in large areas at low cost using polymer-assisted deposition (PAD), where the polymer controls the viscosity and binds metal ions, resulting in a homogeneous distribution of metal precursors in the solution and the formation of uniform metal-organic films. The latter feature makes it possible to grow simple and complex crack-free epitaxial metal-oxides.

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.cut-off frequency | transfer gate G raphene is of considerable interest as a potential new electronic material (1-10). In particular, it has attracted enormous attention for radio-frequency transistor applications owing to its exceptional high carrier mobility, high carrier saturation velocity, and large current density (11)(12)(13)(14)(15)(16)(17). However, the fabrication of high-performance graphene transistors is a significant challenge because conventional steps in the device-fabrication process often introduce undesired damage into graphene lattice, degrading its electronic performance or resulting in nonideal device geometry with excessive parasitic capacitance or serial resistance (18)(19)(20). The recent development of self-aligned graphene transistors with nanowire gates can address these challenges, and has enabled graphene transistors with the highest intrinsic cutoff frequency-up to 300 GHz (14). Moving forward to the terahertz regime requires high-quality graphene material, damage-free dielectric integration strategy, and self-aligned device layout. The strategy of physical assembling nanowire gate is promising for addressing the latter two problems. On the other hand, the scalability of this approach is complicated by the requirement of unconventional nanowire-assembly processes. Instead of fighting with the difficulty of nanowire assembly, here we report a scalable approach to high-performance graphene transistors by transferring lithographically patterned gate stacks onto graphene as the selfaligned top gate to demonstrate the highest cutoff frequency (up to 427 GHz). Fig. 1 illustrates our approach to fabrication of the self-aligned graphene transistors with transferred gate stacks. A 50-nm gold thin film is first deposited on a Si∕SiO 2 substrate by e-beam evaporation. This gold film is served as the sacrificial substrate in the transferring process. Subsequently, we build the (Al 2 O 3 ∕Ti∕Au) gate stacks on to...

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy.