Multi-port SRAMs are essential for caches and shared data structures, especially in modern multi-core SoCs. The Fin-FET device, which offers high threshold voltage and high on/off current ratio, is a promising candidate for multiport SRAMs for fast read/write speed, high cell density, and low power consumption. In this paper, we perform the first study of multi-port FinFET SRAMs, including the double-ended multi-port FinFET SRAM and three singleended multi-port FinFET SRAMs with isolated read ports. We evaluate the static noise margin, leakage current, and read/write performance of these structures with the predictive technology model for FinFETs. Our results show that single-ended multi-port FinFET SRAMs with isolated read ports offer improved read stability and flexibility over the double-ended structure at the expense of write performance. By increasing the size of the access transistors, we show that the single-ended structures can achieve equivalent write performance to the double-ended structure for 9% area overhead.

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