Atomic layer deposition (ALD) Co was developed using bis( N,N′ -diisopropylacetamidinato)cobalt(II) as a precursor and NH3 as a reactant, producing pure Co thin films with excellent conformality and nanoscale thickness controllability. In addition to NH3 , the Co films were also deposited by using normalH2 gas as a reactant. Compared to ALD Co using normalH2 , the Co thin films deposited by NH3 showed a higher film quality, a lower resistivity, and a higher density. The Co thermal ALD process was applied to area-selective ALD using an octadecyltrichlorosilane self-assembled monolayer as a blocking layer, which produced 3μm wide Co line patterns without an etching process.

GaN nanowires and InGaN disk heterostructures are grown on an amorphous SiO₂ layer by a plasma-assisted molecular beam epitaxy. Structural studies using scanning electron microscopy and high-resolution transmission electron microscopy reveal that the nanowires grow vertically without any extended defect similarly to nanowires grown on Si. The as-grown nanowires have an intermediate region consisting of Ga, O, and Si rather than SiNx at the interface between the nanowires and SiO₂. The measured photoluminescence shows a variation of peak wavelengths ranging from 580 nm to 635 nm because of non-uniform indium incorporation. The nanowires grown on SiO₂ are successfully transferred to a flexible polyimide sheet by Au-welding and epitaxial lift-off processes. The light-emitting diodes fabricated with the transferred nanowires are characterized by a turn-on voltage of approximately 4 V. The smaller turn-on voltage in contrast to those of conventional nanowire light-emitting diodes is due to the absence of an intermediate layer, which is removed during an epitaxial lift-off process. The measured electroluminescence shows peak wavelengths of 610-616 nm with linewidths of 116-123 nm.

As graphics processing units (GPUs) are broadly adopted, running multiple applications on a GPU at the same time is beginning to attract wide attention. Recent proposals on multitasking GPUs have focused on either spatial multitasking, which partitions GPU resource at a streaming multiprocessor (SM) granularity, or simultaneous multikernel (SMK), which runs multiple kernels on the same SM. However, multitasking performance varies heavily depending on the resource partitions within each scheme, and the application mixes. In this paper, we propose GPU Maestro that performs dynamic resource management for efficient utilization of multitasking GPUs. GPU Maestro can discover the best performing GPU resource partition exploiting both spatial multitasking and SMK. Furthermore, dynamism within a kernel and interference between the kernels are automatically considered because GPU Maestro finds the best performing partition through direct measurements. Evaluations show that GPU Maestro can improve average system throughput by 20.2% and 13.9% over the baseline spatial multitasking and SMK, respectively.

As graphics processing units (GPUs) are broadly adopted, running multiple applications on a GPU at the same time is beginning to attract wide attention. Recent proposals on multitasking GPUs have focused on either spatial multitasking, which partitions GPU resource at a streaming multiprocessor (SM) granularity, or simultaneous multikernel (SMK), which runs multiple kernels on the same SM. However, multitasking performance varies heavily depending on the resource partitions within each scheme, and the application mixes. In this paper, we propose GPU Maestro that performs dynamic resource management for efficient utilization of multitasking GPUs. GPU Maestro can discover the best performing GPU resource partition exploiting both spatial multitasking and SMK. Furthermore, dynamism within a kernel and interference between the kernels are automatically considered because GPU Maestro finds the best performing partition through direct measurements. Evaluations show that GPU Maestro can improve average system throughput by 20.2% and 13.9% over the baseline spatial multitasking and SMK, respectively. CCS Concepts • Computer systems organization → Single instruction, multiple data; • Hardware → Onchip resource management; • Software and its engineering → Multiprocessing / multiprogramming / multitasking

Near-threshold operation has emerged as a competitive approach for energy-efficient architecture design. In particular, a combination of near-threshold circuit techniques and parallel SIMD computations achieves excellent energy efficiency for easy-to-parallelize applications. However, near-threshold operations suffer from delay variations due to increased process variability. This is exacerbated in wide SIMD architectures where the number of critical paths are multiplied by the SIMD width. This paper provides a systematic in-depth study of delay variations in near-threshold operations and shows that simple techniques such as structural duplication and supply voltage/frequency margining are sufficient to mitigate the timing variation problems in wide SIMD architectures at the cost of marginal area and power overhead.