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Energy-dispersive Laue diffraction (EDLD) is a tool for the characterization of singlecrystalline and polycrystalline materials. Using a two-dimensional energy-dispersive detector, both the angular positions and the diffracting energies of the Laue spots can be analysed without additional information, allowing for fast indexing, determination of the crystal structure and the respective lattice parameters. Running the detector at ≈ 400 Hz, a typical data set (≈ 10 min) taken by the single photon counting mode has a size of ten Gigabytes. Up to now, problems such as data transfer, data storage, data reduction and on time data analysis are drawbacks for wider application of this technique. A fast and effective algorithm for processing of these BIG Data is required to overcome the drawbacks and to allow for quality assessment of the running experiment in real time. This paper presents a GPU based tool for energy-dispersive Laue diffraction (EDLD) experiments, named "EDLD-Tool", providing the optimization of geometric parameters of the experiment, autoindexation, online steering, error detection and determination of all crystal parameters considering pnCCD data taken from a single crystal. This tool is exploiting parallel computing technology of the GPU and makes use of many scientific, high performance libraries (i.e. OpenCV, Root-Cern, Eigen and others). As a result, the developed tool allows for data processing in the time frame of few seconds compared to the previous analysis system which requires few hours to process the same amount of data.

The static resource allocation in time-triggered systems offers significant benefits for the safety arguments of dependable systems. However, adaptation is a key factor for energy efficiency and fault recovery in Cyber-Physical System (CPS). This paper introduces the Adaptive Time-Triggered Multi-Core Architecture (ATMA), which supports adaptation using multi-schedule graphs while preserving the key properties of time-triggered systems including implicit synchronization, temporal predictability and avoidance of resource conflicts. ATMA is an overall architecture for safety-critical CPS based on a network-on-a-chip with building blocks for context agreement and adaptation. Context information is established in a globally consistent manner, providing the foundation for the temporally aligned switching of schedules in the network interfaces. A meta-scheduling algorithm computes schedule graphs and avoids state explosion with reconvergence horizons for events. For each tile, the relevant part of the schedule graph is efficiently stored using difference encodings and interpreted by the adaptation logic. The architecture was evaluated using an FPGA-based implementation and example scenarios employing adaptation for improved energy efficiency. The evaluation demonstrated the benefits of adaptation while showing the overhead and the trade-off between the degree of adaptation and the memory consumption for multi-schedule graphs.

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.