Atomic layer deposition (ALD) of hafnium silicate HfxSi1−xO2 thin films from tetrakis(ethylmethylamino)hafnium, tetrakis(ethylmethylamino)silicon, and ozone was accomplished onto 300-mm-diam Si substrates using a hot-wall furnace system with a 50-wafer batch configuration. For 23-nm-thick hafnium silicate, excellent film thickness uniformity with a mean within-wafer uniformity of 0.84% (1σ∕mean) and a wafer-to-wafer thickness uniformity of 0.80% (1σ∕mean) was achieved over the top, middle, and bottom wafers in the full batch process. Over three times enhancement in wafer-per-hour throughput per chamber was observed as compared with a single-wafer ALD module.

An alternative Zr source to tetrakis(ethylmethylamino)zirconium (TEMAZr) was evaluated in this study to develop more thermally robust 300mm ZrO 2 ALD process. It was observed that a transition from ALD to CVD takes place at approximately 340˚C susceptor temperature. This temperature is significantly higher than that for the commonly used TEMAZr-based ALD process by approximately 40˚C. Excellent step coverage of near 100% of ALD ZrO 2 has been achieved in 40:1 aspect ratio structures using this new ZrO 2 ALD process. ZrO 2 ALD films of 5.5nm thickness demonstrated a low leakage current of 2x10 -9 A/cm 2 at 1.2V. The same ALD reactor was also evaluated for the next generation highk components such as SrOx and LaOx.

Although much effort has been expended toward developing alternate dielectrics for use in fabricating ULSI circuits, there is still a need for high quality SiO2 films. In particular, process temperature restrictions have increased the demand for high quality, low temperature SiO2 films.[1] Such films have multiple applications in microelectronics, including use as passivation coatings, interlevel dielectrics, gate dielectrics in metal oxide semiconductor field effect transistors (MOSFETs), thin film transistors, and in devices using dual spacers.[2] Advanced devices at the 65-nm node and beyond are typically fabricated with nickel silicided electrodes—which enable lower junction silicon consumption, lower sheet resistance, and reduced agglomeration, but require subsequent process temperatures to be below 550°C. Also, to prevent movement of the ultra shallow junctions (USJs) during a subsequent thermal cycle, the temperatures for process steps after USJ formation must be kept below 600°C. To meet these needs, we have developed a low temperature (<500°C) SiO2 process that results in excellent dielectric quality.This paper presents results on high-quality chemical vapor deposition (CVD) SiO2 films deposited at temperatures from 200°C to 450°C using a novel proprietary and versatile silicon precursor using oxygen as the oxidizer. Composition, film stress, deposition rate, leakage current density, and step coverage results are presented.

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