Dielectric properties of (Ba0.5Sr0.5)TiO3 and (Ba0.75Sr0.25)TiO3 thin films have been investigated, focusing on the effects of film structure and Ba/Sr compositions on the dielectric properties. Dielectric constant of the films increased with increasing grain size and with improvement in film crystallinity. For the 50-nm-thick films deposited at 660° C, the dielectric constant of 400 for the (Ba0.5Sr0.5)TiO3 film is larger than that of 320 for the (Ba0.75Sr0.25)TiO3 film. This indicated that dielectric constant is affected by the ratio of Ba/Sr composition. Leakage current density of less than 1×10-7 A/cm2 at 1 V and SiO2 equivalent thickness of 0.38 nm are measured at 120° C for 660° C-deposited (Ba0.5Sr0.5)TiO3 film of 30 nm in thickness. The (Ba0.5Sr0.5)TiO3 film has the possibility for application to generations beyond 256 Mbit dynamic random access memories.

We demonstrated highly reliable Cu interconnects using a high-quality silicon nitride film grown at temperatures below 300 C. The low-temperature silicon nitride (LT-SiN) film, which was used as a Cu-diffusion barrier layer and a final passivation layer, was deposited at 275 C by plasma-enhanced chemical vapor deposition at a low SiH 4 flow ratio. The low SiH 4 flow ratio was due to the use of a highly dilute nitrogen flow, leading to the generation of many nitrogen radicals or ions in the plasma. These radicals or ions might reduce the hydrogen concentration and defect density of the film. As a result, a stoichiometric silicon nitride (Si 3 N 4 ) film with a low hydrogen concentration was successfully obtained. By applying this LT-SiN film in 130-nm-node Cu interconnects for magnetoresistive random access memory, highly reliable via-hole electromigration (Via-EM) and line-to-line time-dependent dielectric breakdown (TDDB) characteristics were obtained.

A novel capacitor technology has been developed for 0.15 µm embedded dynamic random access memory (DRAM). Platinum as electrodes and barium strontium titanate (BST) as dielectrics are used in the capacitor. The BST dielectrics is a stack of two layers. The nucleating bottom layer is deposited by sputtering and the top bulk layer is deposited by chemical vapor deposition (CVD). The two-step deposition process is established with high reliability without N2 high-temperature annealing. Moreover, both thermal stability and reductive stability of the BST capacitors are improved by introducing modulated oxygen-doping into the Pt top electrodes. The degradation mechanism of the BST capacitors by annealing in the back end process was revealed. Oxygen atoms doped into the top electrode diffuse to the interface between the bottom electrode and the metal nitride barrier layer, and oxidize the metal nitride. The modified BST capacitors maintained low leakage current and sufficient capacitance after 500°C N2 annealing and 400°C H2 annealing. These BST capacitors have been integrated into the 0.15 µm rule-embedded DRAM having a capacitor under bit-line (CUB) structure and four-level metallizations.

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