A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.

A Resistor ladder is an important circuit block for parallel architecture analog-to-digital converters (ADCs). The output of ADC suffers from distortion due to kickback noise from comparators when the bias current of the resistor ladder is reduced to reduce its power dissipation. A technique of distortion compensation that cancels kickback noise by injecting compensation current to the resistor ladder has been known to overcome this problem. This technique, however, did not consider that kickback noise depends on the sampling frequency and variability of resistors. Therefore, we propose an automatic circuit for distortion compensation that detects the amount of kickback noise and properly adjusts the compensation current. The simulation results demonstrated that distortion could be reduced with the proposed technique even when the changes in sampling frequency and deviations in the resistor occurred.