Cu interconnects are used in semiconductor devices and their dimensions are downscaled markedly. Cu interconnects are fabricated by a damascene process, and it becomes difficult to fill Cu into trenches and vias structures by electroplating below the 20 nm feature size. We evaluated the process integration for Cu interconnects using a Co wetting layer by chemical vapor deposition (CVD), a Cu seed by magnetic-field-assisted ionized sputtering (MFIS) and a Cu reflow technique. The properties of a CVD-Co film, such as composition, resistivity, step coverage, and adhesion between Cu and Co, were investigated. By using CVD-Co as the wetting layer, the properties of Cu gap filling in a trench structure were improved, and the filling of Cu into a 14-nm-wide trench structure was achieved.