In this paper, we present a new process flow to increase cell capacitance in planar dynamic random access memory cells designed for system-on-chip applications. Silicon dioxide of shallow trench isolation ͑STI͒ under capacitor electrodes is recessed to increase cell capacitance. It appears that the cell capacitance is increased to 25% when the STI recess is 0.15 m. The recession slightly decreases junction leakage current due to annealing of defects and also relief of STI stress. These combined effects increase refresh time about 50% in 1 Mb memory array. The distribution of breakdown voltage in capacitor oxide shows similar behavior compared with samples without STI recessed. Also, the lifetime of the capacitor oxide evaluated from the Weibull method exceeds 2000 years.There has been increasing interest of embedded dynamic random access memory ͑DRAM͒ for system-on-chip ͑SoC͒ application. 1-3 The advantages of embedding DRAM to logic circuits are increased bandwidth, reduced power consumption, and small die size. However, there are critical problems such as degraded refresh time in DRAM cells and low yield caused by increased processing steps when one embeds standard DRAM cells to logic processes. This is caused by incompatibility between DRAM and logic processes. While the DRAM process focuses on the reduction of cell size with sacrifice of device performance, the logic process mainly focuses on enhancing device performance by using processes such as dual-gate transistors, salicide, and multilevel metals. Unfortunately, these steps in the logic process degrade the refresh time of DRAM cells and also reduce total yield due to increased process steps. 4,5 Recently, planar DRAM cells are investigated to solve these problems. Planar DRAM cells consist of a pass transistor and a metal-oxide-semiconductor ͑MOS͒ capacitor. Although its cell size is normally 6-8 times larger than stack or trench type DRAM cells, it uses a standard logic process and thus enables use of a standard logic library and intellectual properties. 6 The weak point of planar DRAM cells compared with stack cells is a reduced cell capacitance because it uses only two dimensions. Although one can increase cell capacitance by increased cell area, packing density is reduced due to increased die size. The other way could be to use thinner gate oxide or high dielectric constant material such as silicon nitride or tantalum oxide. However, it becomes difficult to implement this in a logic compatible process.In this paper, we present a new process flow to increase cell capacitance in planar DRAM cells by partial recess of shallow trench isolation ͑STI͒. It appears that the cell capacitance is increased up to 25% when the recessed depth is 0.15 m. The measured reliability of the capacitor oxide has no difference compared with the sample without STI recession. These combinations enhance the refresh time of DRAM cells. Figure 1 shows a vertical structure of the DRAM cell used in this study. It has a p-MOS access transistor and a planar capacitor. The main char...

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In this letter, process technology and cell characteristics of a newly developed compact electrically erasable programmable read only memory cell are described. The cell has spacer select gates on both side walls of floating gate and this gives a very small cell size as well as relief of topology during contact formation. The cell size is 0.95 m 2 with 0.18 m logic process. The cells are programmed and erased by Fowler-Nordheim tunneling. It appears that programming requires 3 ms at 16 V while erasing requires 2 ms at 14 V. It is shown that the cells have very uniform distribution of both programmed and erased threshold voltage. It is also shown that the cell endures up to half million cycling tests. Index Terms-Electrically erasable programmable read only memory (EEPROM) cell, embedded electrically erasable programmable read only memory (EEPROM), endurance, Floating-gate, Fowler-Nordheim (FN) tunneling, select gate.

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