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DRAM's process technology has been scaled down rapidly and the size of the wafer has reached 300mm. Despite being fabricated on the same wafer, two chips may have very different characteristics if the one is from the center and the other is from the edge of wafer. Therefore, the process skew reduction is becoming more important as the process is scaled down under 100nm. The dynamic voltage scaling scheme (DVS) has already won huge popularity in mobile applications with limited battery life. Various dynamic voltage scaling techniques for μ-processors have also been developed during the last decade [1]. However, selection of the power supply voltage for DRAM is dictated by the application or the worst process skew that guarantees the performance of DRAM. This paper proposes a self-dynamic voltage scaling (SDVS) technique for DRAM to overcome the process variation and reduce the power consumption according to the operating frequency.DRAM has several internal voltage levels which are VPP for driving word line, VBLP for bit line pre-charge, VCP for cell capacitor plate, VCORE for data store and VBBW for off-state bias of word line to reduce the off-leakage. These internal voltages have to be used to satisfy the data store operating and keep the charges during retention time. Therefore, it is hard to change these internal voltages for DRAM core. On the other hand, performance of peripheral circuits is closely connected with the FO3 (Fan-Out 3) delay. Therefore, the internal voltage level for peripheral circuits can be easily adapted according to the operating frequency and the process skew.Recently, application systems with DVS are being widely used to reduce power consumption. However, they did not take the process condition of DRAM into account. The proposed SDVS technique uses two parameters; one is the process skew of DRAM component and the other is the frequency of the CLK fed to DRAM. The proposed SDVS block diagram is shown in Figure 28.8.1. The SDVS generates the signals UP and DN for the voltage regulator after measuring the tRDLY in terms of the number of CLK cycles that comes from the controller. The tRDLY copies the timing delay between the CLK input and the DQ output. In case of slow skew, the signal UP is enabled. So the internal voltage for peripheral circuits (VPERI) is increased to improve the performance. Otherwise, if the operating frequency is slow enough to ignore the reduced timing margin, the SDVS maintains the previous VPERI or lowers the VPERI by the signal DN.By the help of SVDS, each DRAM can have an optimal VPERI that lowers the leakage and active standby current. The SDVS determines the VPERI during power up sequence or self-refresh exit condition. Figure 28.8.2(a) shows the relative FO3 delay distribution within a wafer.Randomly selected 450 samples are used for measurement. The slowest FO3 delay is improved by 20% when VPERI is raised from 1.1V to 1.2V. At VPERI of 1.1V, the FO3 delay variation is almost 30% even if the measured samples are from the same wafer. The more wafers fabricated,...

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