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Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. In this paper, we propose two routability optimization methods to implement designs even with very low (or high) aspect ratio and high area utilization. First, we find the best assignment of non-uniform placement utilization through convolutional neural network model, and cell placement is performed while respecting the placement utilization. This allows many cells to be spread out over the entire design rather than being centered. The experiments show that most overflows of 16.5% occurring in cell placement are removed with 23.1% reduction in wire length; this is the result of further improving overflow of 9.8% compared to a conventional method. In the second, some flip-flops are selectively stacked to reduce the routing resources used for clock routing. U-Net model is built with graph attention network to predict the congestion after clock tree synthesis, and the flip-flops in highly congested areas are selected for stacking. The proposed method improves the overflows, which occurs after clock tree synthesis, by 22.1%.

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