Electric-field-driven spintronic devices are considered promising candidates for beyond CMOS logic and memory applications thanks to their potential for ultralow energy switching and nonvolatility. In this work, we have developed a comprehensive modeling framework to understand the fundamental physics of the switching mechanisms of the antiferromagnet/ ferromagnet heterojunction by taking BiFeO 3 /CoFe heterojunctions as an example. The models are calibrated with experimental results and demonstrate that the switching of the ferromagnet in the antiferromagnet/ferromagnet heterojunction is caused by the rotation of the Neel vector in the antiferromagnet and is not driven by the unidirectional exchange bias at the interface as was previously speculated. Additionally, we demonstrate that the fundamental limit of the switching time of the ferromagnet is in the subnanosecond regime. The geometric dependence and the thermal stability of the antiferromagnet/ferromagnet heterojunction are also explored. Our simulation results provide the critical metrics for designing magnetoelectric devices.

As spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the nextgeneration low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ) properties needed to achieve sub-ns, and ~fJ write operation when integrated with CMOS access transistors. In this paper, a 2T-1MTJ cell-level modeling framework for in-plane type Y SOT-MRAM suggests that high spin Hall conductivity and moderate SOT material sheet resistance are preferred. We benchmark write energy and speed performances of type Y SOT cells based on various SOT materials experimentally reported in the literature, including heavy metals, topological insulators and semimetals. We then carry out detailed benchmarking of SOT material Pt,-W, and BixSe(1-x) with different thickness and resistivity. We further discuss how our 2T-1MTJ model can be expanded to analyze other variations of SOT-MRAM, including perpendicular (type Z) and type X SOT-MRAM, two-terminal SOT-MRAM, as well as spin-transfer-torque (STT) and voltagecontrolled magnetic anisotropy (VCMA)-assisted SOT-MRAM. This work will provide essential guidelines for SOT-MRAM materials, devices, and circuits research in the future.

D. Zhang, et al., "Bipolar electric-field switching of perpendicular magnetic tunnel junctions through voltagecontrolled exchange coupling" (2019)

The switching dynamics of a single-domain BiFeO3 thin film is investigated through combining the dynamics of polarization and Neel vector. The evolution of the ferroelectric polarization is described by the Landau-Khalatnikov (LK) equation, and the Landau-Lifshitz-Gilbert (LLG) equations for spins in two sublattices to model the time evolution of the antiferromagnetic order (Neel vector) in a G-type antiferromagnet. This work theoretically demonstrates that due to the rotation of the magnetic hard axis following the polarization reversal, the Neel vector can be switched by 180⁰, while the weak magnetization can remain unchanged. The simulation results are consistent with the ab initio calculation 1 , where the Neel vector rotates during polarization rotation, and also match our calculation of the dynamics of order parameter using Landau-Ginzburg theory 2 . We also find that the switching time of the Neel vector is determined by the speed polarization switching and is predicted to be as short as 30 ps.

In this article, we present a cross-layer optimization and benchmarking of various spintronic memory devices, including spin-transfer-torque magnetic random access memory (STT-MRAM), spin-orbittorque (SOT) MRAM, voltage-controlled exchange coupling (VCEC) MRAM, and magnetoelectric (ME) MRAM. Various material, device, and circuit parameters are optimized to maximize array-level READ and WRITE performances and to benchmark spintronic devices against static random access memory (SRAM). It is shown that the optimized parameters, such as magnetic tunnel junction (MTJ) oxide thickness or transistor size, are quite different for various device options. The optimal oxide thickness of VCEC-MRAM is 1.6 nm because it is a voltage-controlled device; thus, thicker oxide gives smaller READ energy-delay product (EDP), whereas, for STT-MRAM, the optimal oxide thickness is 1.3 nm to keep the WRITE voltage low while avoiding READ disturbs. In addition, we find that the co-optimization of material, device, and circuit analyses are critical because it is not enough to identify the most promising material for various device options with only materialor device-level metrics. For instance, SOT materials with the highest spin conductivity may not result in the best array-level WRITE performance because of their large resistivity and, in some cases, READ disturb issues. We also present a new design and cell layout for ME-MRAM in which the number of access transistors depends on the WRITE voltage. The benchmarking results show that SOT-MRAM can be fast and low energy but would suffer from a 25% larger cell area compared with STT-MRAM. VCEC-MRAM can be denser than STT-MRAM (2T1MTJ) and dissipate less energy but would suffer from slower READ operations because of its large oxide thickness. ME-MRAM can be fast, low energy, and dense compared with all other options. INDEX TERMS Magnetoelectric (ME), nonvolatile memory, spintronics, spin-orbit torque (SOT), spin-transfer torque (STT), voltage-controlled exchange coupling (VCEC).