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In this paper, one low-temperature direct Cu bonding structure is demonstrated using metal passivated layers. With the protection of Cu bonding layer, the bonding temperature can be reduced to meet low thermal budget requirement. Direct wafer-level Cu bond scheme with Pd passivation is successfully demonstrated at 150°C. Electrical performance along with the material analysis and reliability tests of passivated Cu bonded structures is presented. Furthermore, reliability assessments, including current stressing, temperature cycling, and unbiased highly accelerated stress test, imply excellent stability without electrical degradation. Diffusion behavior between passivation Pd and Cu layers is surveyed, and the corresponding mechanism is discussed as well. The low-temperature Cu/Pd-Pd/Cu bonded structure presents good bond quality and electrical performance, indicating a great potential for 3-D integration applications. Index Terms-3-D integration, Cu bonding, passivation.0018-9383

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Low-temperature (170°C) Cu/In wafer-level and chip-level bonding for good thermal budget has been successfully developed for 3-D integration applications. For the well-bonded interconnect, Cu 2 In and Cu 7 In 3 phases with high melting temperature of 388.3°C and 632.2°C can be formed, indicating high thermal stability. In addition, stable low specific contact resistance of bonded interfaces can be achieved with the values of approximately 0.3 × 10 −8 -cm 2 . In addition to exceptional electrical characteristics, the results of electrical reliability assessments including current stressing, temperature cycling, and unbiased HAST show excellent stability of Cu/In bonds without obvious deterioration. The low-temperature Cu/In bonding technology presents good bond quality and electrical performance, and possesses a great potential for future applications of 3-D interconnects. Index Terms-3-D integration, Cu/In bonding, interconnect.