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A low-voltage inverter-based sigma-delta modulator (SDM) based on a three-phase clock technique is presented. The three-phase clock is proposed to mitigate a performance degradation due to a gate leakage current in advanced process nodes, which reduces noise introduced by the charge injection at the end of a sampling phase and an integrating phase. Simulation results in a 65 nm CMOS process show that the spectrum characteristics of the SDM match well the MATLAB model and achieve 5.1-dB enhancement in the signal-to-noise and distortion ratio performance compared to a traditional inverter-based SDM implementing the uniform loop filter and the same oversampling ratio.

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