Abstract:In many applications, the quality of data gathered by sensor networks is directly related to the signal-to-noise ratio (SNR) of the sensor data being transmitted in the networks. Different from the SNR that is often used in measuring the quality of communication links, the SNR used in this work measures how accurately the data in the network packets represent the physical parameters being sensed. Hence, the signal here refers to the physical parameters that are being monitored by sensor networks; the noise is due to environmental interference and circuit noises at sensor nodes, and packet loss during network transmission. While issues affecting SNR at sensor nodes have been intensively investigated, the impact of network packet loss on data SNR has not attracted significant attention in sensor network design. This paper investigates the impact of packet loss on sensor network data SNR and shows that data SNR is dramatically affected by network packet loss. A data quality metric, based on data SNR, is developed and a cross-layer adaptive scheme is presented to minimize data quality degradation in congested sensor networks. The proposed scheme consists of adaptive downsampling and bit truncation at sensor nodes and intelligent traffic management techniques at the network level. Simulation results are presented to demonstrate the validity and effectiveness of the proposed techniques.

We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 lm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of *50 ps width with *17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Gigasample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.

This paper investigates techniques to minimize process-variation induced performance degradation in pipeline ADCs via circuit reconfiguration. By taking advantage of the modularity existing in pipeline ADC circuits, this work introduces a configurable switch network that makes it possible to move more accurate pipeline circuits to the preceding stages along the signal processing path. The reconfiguration feature also adds online testing capabilities and enhances fault-tolerance of pipeline ADCs. An implementation of reconfigurable 10-bit 1.5-bit per stage pipeline ADC circuit is presented. Circuit simulation shows both improved circuit performance and fault tolerance are achieved by circuit reconfiguration. 1