No abstract

In order to significantly improve warpage of a PoP bottom package, Shinko developed an enhanced PoP structure. The inclusion of a support material attached to the backside of the flip chip die and over molded resin is the structure's key attribute. By adjusting the balance of each material (mold resin, substrate and support material thickness), we can better control warpage at both room temperature and reflow temperature. This enhanced thin PoP structure can be easily incorporated into a standard assembly process with existing equipment sets. This paper describes simulation results, along with measured warpage characteristics of the new package.

We develop a package that ensures quality complying with AEC-Q 100 Grade 2 which is in-vehicle quality from various flip chip mounting methods and bump sealing technology with underfill resin and mold resin. FC CSP with heat spreader mounted on the product which has started mass production since last year is in the lineup, The heat dissipation can be improved by attaching the heat spreader directly to the chip backside which are heat sources and the Thermal Interface Material (TIM), using our assembly technology of flip chip mounting and molding the periphery while exposing the chip backside. By adjusting the Coefficient of Thermal Expansion (CTE) and thickness of the material, we realize low warpage and low coplanarity at reflow temperature and product use temperature environment and reduce package displacement behavior, we will improve the secondary mountability to the motherboard and provide reliable packages. Furthermore, it can be applied to SiP modules. It is also possible to construct multiple chip modules by mounting multiple ICs or placing low-passive components around them. We will consider heat spreader mounting on multiple ICs that generate heat, and metal coating on the entire SiP module to have a structure that achieves both heat dissipation and electromagnetic shielding as a future idea.

One of the challenges in using very thin die, which is needed in thin package, is how to dice it cleanly without chipping, delamination of fragile low-k insulation material and contamination of bonding pads. A narrow scribe line is also highly preferable for high wafer area utilization. The authors developed a novel "grooving and stealth laser process" to satisfy all of these criteria. Grooves are formed on test pads in die sawing area by a grooving laser beam, and then a stealth laser beam is focused into the bulk silicon, causing defect regions in the bulk silicon. Dicing tape is expanded so that the wafer breaks into separated dice.