A digital front-end with digital compensation is designed and implemented for lowcomplexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a > 40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.

A system simulator is proposed and developed, which can help to optimize design parameters and hence minimize the number of collisions. In order to search the optimal design parameter combination which meets the user requirement, the proposed simulator has some knobs: partitioning between software and hardware, scheduling the operations in the system, and memory merging, all of which can be adjusted to predict collisions and search the optimal architecture. Also, design parameters can be adjusted sequentially to cover all design options and estimate the predicted performance for each option. The proposed system simulator is evaluated with an example signal processing algorithm, orthogonal matching pursuit (OMP) algorithm. Performances of four cases of the OMP algorithm are predicted by the proposed simulator and in turn are compared with the actual performances on ZedBoard. The proposed simulator can predict the performance of heterogeneous systems on chips with under 5% error for all the candidate architectures for OMP while taking the system bus and memory conflicts into account. Moreover, the optimized heterogeneous SoC architecture for the OMP algorithm improves performance by up to 32% compared with the conventional CAG-based approach. The proposed simulator is verified that the proposed performance estimation algorithm is generally applicable to estimate the performance of any heterogeneous SoC architecture. For example, the estimation error is measured to be no more than 5.9% for the convolutional layers of CNNs and no more than 5.6% for the LDPC-coded MIMO-OFDM. In addition, the optimized heterogeneous SoC architecture improves performance by up to 48% for the third convolutional layer of AlexNet and 56% for the LDPC-coded MIMO-OFDM. Lastly, compared with the conventional simulationbased approaches, the proposed estimation algorithm provides a speedup of one to two orders of magnitudes.