Ahfrad-Thispaper presents a cooperative compact genetic algorithm (CnCGA). The CoCGA is developed fmm the mmpaa G A and pmposed to he wed lirr intrinsic emlval~le hardware, The concept and algorithm of the CoCGA are presentd. The hard war^ implementation of the C O M A and C G h were carried out. The standard test functions were selected lo rneasllpe the eflectiveness wl the CoCGA. The experimental results sikmificanily shrrws that the CrlCGA rmtprr4rrms the normal compact (;A both in s p e d and quality with acceptable usage of hardware w u r c e s for modern-day FPGAs. Evolvable Hardware (EH) is an emerging research area in Evolutionary Computalion (EC). There am a number of methods and lechniques that propose to apply the Genetic Algorithm (CAI, Evolutionary Strategy (ES), and Genetic Programming (GP) to be implemented in hardware, especially implementalion onro FPGAs ar other reconfigurable devices [I], [Z], [ill. l'here are two approaches Tor Lhe design of EH: extrinsic and intrinsic [3], [S].For extrinsic EH, the evolulionary process is perromed off-line. Then the results is downloaded onto he hardware. On the contrary, for the intrinsic EH, the evolutionary process is perrormed wholly or paslly in hardware [h]. [7], [El, [g]. H~wever, in order to accomplish the intrinsically on-line evolving in hardware and to utilize hardware resource etficiently, a challenging question is how tu modiry or invent efficient and improved GA or EA algorithms dial can be erfecdvely implemented in hardware.The trend towards the increasing or density and price per performance or currenl FPGAs due to advanced semiconducLor process r.ec11noiogy provides an opportunity lor designers and researchers to use lager and raster FPGAs for Evolvable Hardware [I 11, [I 21. With this trend of WGA technology development, ~11e concept of implementing a group or parallel processing unils for EH in a single FPGA chip is reasible [8], [I 01. In this paper. the coopera~ive compact genetic algorithms (CGA) is proposed and it's hardware implementalion is explored as the compact GA is one of ihe key algorithms suihhle -For hardwm implementation [16]. Contrary to the Simple GA (SGA), the compact GA is more suitable for hardware implementalion due to using probability vectors [I 71, [I h]. The CGA manipulales the probability vector instead of operating on Ehe aclual population. This dramatically reduces a number orbits and memory required to store the population. With this representation, it is practical to use only registers implemented using DFlip-Flops in digital circuits. Thus, i i eliminates rhe nmd for Random Access Memory (RAM). The experiment shows ~l l a~ Lhe hardware Compact GA is a1 least 1000 limes raster lhan a soriware version [ I 71.Even lhougli rhe compact GA has advanlage Tor hardware irnpl.ernenialion, but unrurtunately, the basic compact GA lacks of sufficient search power for EH applications that requires accuracy and faster processing time. Therefore, the CGA has been improved hy adding more techniques like elitism, mumtion, and c...

Abstract

This paper presents a hardware design of an ultrasound imaging system for transmitting pulses and acquiring echo signals to/from individual elements of an array transducer. Since most of the ultrasound imaging systems in the market provide only image files after reconstruction, the presented hardware can be controlled by a computer in order to transmit pulses in specific patterns to transducer elements and in order to access the data from individual transducer elements. It benefits the research and development of new algorithms for beamforming, image reconstruction, and other applications, such as elastography and ultrasonic transmission tomography.