In the conventional cross-coupled CMOS magnetic fieldeffect transistor (MAGFET) pair, at least one MAGFET is self-biased. The output swing at. the self-biasd end is then inevitably limited to the threshold voltage of the self-biased MAGFET. This problem emerges for bipolar magnetic field sensing. In this paper, we propose a bias-adaptive voltage level shifter to remove the direct self-bias connection between the gate and the drain and to adjust the operating point at the output node, so as to achieve symmetric yet maximum positive and negative output swings. The improvements have been verified by HSPICE simulation.

A CMOS magnetic latch for digital magnetic field detection is reported. It is based on a single split-drain magnetic field-effect transistor with a positive feedback imported by a pair of lateral floating gates. The magnetic latch achieves its maximum magnetic sensitivity when latch-up takes place. A linear equation is used to model the positive feedback and the latch-up process. By imposing a reset-evaluation mechanism, the magnetic latch is evaluated for digital magnetic pattern detection. Experimental results show that the minimum detectable magnetic flux density for the magnetic latch could be down to less than 0.1 mT with low bit error rate.Index Terms-CMOS magnetic latch, magnetic field-effect transistor (MAGFET), magnetic field measurement, magnetic pattern recognition.

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